Reducing DDR4 Board Failures and Design Optimisation Time
SECO has adopted a design flow that minimises the engineering effort required to set up simulations. It provides an entire high-speed digital design workflow and offers a unique capability to use the same measurement science for both simulation and hardware verification stages. As a result they have been able to reduce design time and improve yield dramatically.

The presentation covers:

  • Extract high-accuracy electromagnetic (EM) models of the PCB
  • Perform efficient system simulation of the buses
  • Make sure the design matches compliance testing
Duration: 56 minutes
Available On Demand




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PRESENTERS
Alessandro Pali
Alessandro Pali
PCB Design & Hardware Validation
SECO S.p.A
Lorenzo Forni
Lorenzo Forni
Signal & Power Integrity Senior Designer
SECO S.p.A

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