Optimizing Capacitor Selection and Placement for Power Integrity

Simulating PCIe Gen5 for Embedded System Design

Part of Simulating for High-Speed Digital Insights series

January 13, 2022 | 10:00 AM PT / 1:00 PM ET

Leveraging past power delivery designs or relying on vendor data sheets often leads to failures late in your design. These two design approaches can result in costly retrofits or schedule slippage with multiple re-spins. What if you could start early in the design to select the right capacitors to meet a desired power integrity target impedance? See how to utilize 3DEM simulation to understand the impact of parasitics and optimize your design with a digital twin instead of trial and error with hardware.

Key Learnings:

Why Electromagnetic (EM) simulations get the parasitics right and SPICE does not
How inductance drives the selection of capacitors
How to avoid L/C resonances when placing decoupling capacitors
Design tricks to minimize the quantity of decoupling capacitors

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PRESENTERS

Heidi Barnes

Power Integrity Product Owner

Keysight Technologies