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Simulating for High-Speed Digital Insights
High-Speed Digital Chip Board
The latest technology for serial links and memory interfaces is getting into the multi-gigabit range. We see them adopting multi-level modulations and more advanced data recovery methods. As a result creating a stable and compliant design is more challenging than ever before and standard signal integrity analysis is no longer sufficient.

Keysight is offering a design flow, which gives you all the insights you need. In this webinar series, our experts will cover leading edge applications of Keysight's premier SerDes and Memory simulation platform, PathWave ADS, with respect to Signal Integrity, Power Integrity and EMI simulation and analysis.

Select one or more webinars of interest, then submit registration form.
Optimizing Capacitor Selection and Placement for Power Integrity with Heidi Barnes
Original Broadcast Date: January 13, 2022 | Now Available On-Demand
Avoid costly retrofits or schedule slippage with multiple re-spins. Start early in the design to select the right capacitors and meet a desired power integrity target impedance. Learn how to utilize 3DEM simulation and understand the impact of parasitics and optimize your design with a digital twin. Learn more
Conducted EMI Simulations Made Easy with PathWave ADS with Heidi Barnes
Original Broadcast Date: February 10, 2022 | Now Available On-Demand
The automotive industry applies stringent requirements for EMI with CISPR 25 to avoid disturbances in a vehicle. You will want to capture any issue with your design prior to building hardware. However, SPICE is not accurate enough and general-purpose EM simulators are time consuming and complex to use. Learn how to explore and mitigate EMI noise sources with PathWave ADS with PIPro. Learn more
Generating AMI Models for SerDes Applications
Original Broadcast Date: July 14, 2022 | Now Available On-Demand
AMI (Algorithmic Modeling Interface) is the industry standard for SerDes transmitter and receiver models. It includes equalization, and CDR (Clock Data Recovery) and helps to simulate the overall channel and to accurately determine BER (Bit Error Rate). In this webinar, we show an easy-to-use workflow to build and use AMI models. Learn more
Perform Simulation-Based, Virtual Compliance Tests for (LP)DDR
November 15, 2022 | 10:00 a.m. PT / 1:00 p.m. ET
Due to ever increasing data rates there is less design margin given to memory design engineers. You will have to make sure that your implementation is compliant to specifications. In this webinar, we will walk through the compliance tests and design exploration with several memory standards. Learn more
Simulating PCIe Gen5 for Embedded System Design
Original Broadcast Date: December 16, 2021 | Now Available On-Demand
Designers need to balance material selection and PCB fabrication options, together with design strategies for vias, connectors and channels. This webinar covers a simulation process that SECO Italy has undertaken to successfully design an embedded system with a small form-factor, and the right price-point. Learn more
Analyzing Memory Bus to Meet with DDR Specifications
Original Broadcast Date April 14, 2022 | Now Available On-Demand
With memory getting into the multi-gigabit range, the design margins are tighter due to higher crosstalk between vias and traces. Optimizing your design and testing it against specifications is critical. We will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to design with them. Learn more
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