Introduction of EP-Scan for Digital Developers

3 Ways to Optimize Signal Integrity in Your Design Flow

Time to market is crucial to the overall success of modern electronic devices. Schedules keep shrinking, new designs are more complex, and hardware engineers are pressured to squeeze out inefficiencies from workflows.

Signal Integrity (SI) analysis is a key step that must be performed and documented properly to avoid costly design flaws. To be successful, hardware engineers cannot afford to wait until final verification for signal integrity analysis results. Performance must be validated regularly as designs evolve to avoid bottlenecks.

During this webinar we will cover how to identify SI issues and to perform electromagnetic (EM) simulation of signal nets, channel return loss, insertion loss, and impedance Time-Domain Reflection (TDR).

In this webinar you will learn how to:

Fix three common signal integrity issues in your printed circuit board layout
Quickly obtain EM results
Analyze your layout as if it has been manufactured

Register now to maximize your productivity and reduce the time to market

Original Webinar Date: March 22, 2023

Time: On-Demand

Duration: 25 minutes

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PRESENTERS

Chun-ting "Tim" Wang Lee, Ph.D.

Signal Integrity Application Scientist

Keysight Technologies