High-Speed Digital Webinar Series
High Speed Digital
With electronic systems and networks getting more complex every day, it is important to understand the fundamentals of high-speed digital design and know when to use the right tool for the job. Get real-world examples of common industry design problems and how to make sure to choose the right unit and performance level to address and prevent these problems. Whether you are new to high-speed digital design or a seasoned veteran, the goal is to give you the knowledge to take to the lab and use immediately for faster time to test and increase confidence in your digital designs.
Select one or more webinars of interest, then submit registration form.
Advanced Testing Challenges at 32GBaud PAM4 with PCIe® 6.0
Original Webinar Date: February 15, 2022
This webinar will help you better understand some of the key challenges of moving from non-return-to-zero also known as NRZ to PAM4 technology along with new measurement requirements for transmitter and receiver testing.
Next Gen Development in Type-C Ecosystem
Original Webinar Date: February 22, 2022
We will cover the latest updates in the Type-C Ecosystem that includes USB, Display Port (DP), and Thunderbolt. In this webinar, you should learn the differences between testing Thunderbolt™ 3 & 4, USB4®, and DP 2.0, how to avoid pitfalls when testing next-gen type c technologies, and what happens after USB4. 
Physical Layer Validation Challenges of Characterizing 100Gbps/Lane Designs
Original Webinar Date: March 17, 2022
This webinar will be a practical discussion of IEEE 802.3ck (100gbps/lane) physical layer conformal testing for both Tx and Rx. 100G silicon is merging from the early specifications and a world of simulation. We will help bridge the gap between simulation and physical layer evaluation of SERDES design and conformance testing. 
Solving Your Forward Error Correction Problems
Original Webinar Date: March 24, 2022
Forward Error Correction (FEC) can effectively eliminate data loss (frame loss) in systems with moderately high Bit Error Rates (BER) of 1E-4or more. However, in real systems, errors sometimes occur in bursts and can lead to FEC failure and non-zero frame loss ratio (FLR). The key takeaways from this presentation are that your test tools can work in the presence of Forward Error Correction and that new tools exist that make debugging FEC problems easier. 
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