High Speed Digital Virtual Seminar Tour

High-Speed Digital Virtual Seminar Tour - Canada

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NOW AVAILABLE ON-DEMAND

Western Canada - Original Webinar Date: November 30, 2021

Eastern Canada - Original Webinar Date: December 2, 2021

OVERVIEW

With electronic systems and networks getting more complex every day, it is important to understand the fundamentals of high-speed digital design and know when to use the right tool for the job. Get real-world examples of common industry design problems and how to make sure to choose the right unit and performance level to address and prevent these problems. Whether you are new to high-speed digital design or a seasoned veteran, the goal is to give you the knowledge to take to the lab and use immediately for a faster time to test and increase confidence in your digital designs.

AGENDA AND TIMESTAMPS

00:00:00 - Introduction
00:02:30 - Advanced Testing Challenges at 32GBaud Pam4 with PCIe 6.010:45 a.m. - 15 min break
01:30:00 - Next Gen Development in Type-C Ecosystem
03:00:00 - Physical Layer Validation Challenges of Characterizing 100 Gbps/lane Designs
04:00:00 - Solving Your Forward Error Correction Problems

MORE ABOUT THE SESSIONS

Advanced Testing Challenges at 32GBaud Pam4 with PCIe 6.0

PCI Express 6.0 doubles Gen5’s data rate achieving a maximum data throughput of 64GT/s. It does this without needing to increase the bandwidth of the Gen5 channel by utilizing PAM4, multi-level signaling which allows PCIe 6.0 to transmits two data bits per symbol. Nevertheless, PAM4 ushers new challenges in testing at the physical layer and new measurements will need to be made to PCIe Gen6 silicon such as SNDR and multi-edge jitter. This session will help you better understand some of the key challenges of moving from NRZ (non-return-to-zero) to PAM4 technology along with new measurement requirements for transmitter and receiver testing. This seminar leverages test data from Keysight’s pathfinding efforts supporting the development of PCIe Express 6.0 technology along with similar signaling approaches used in the IEEE 802.3 and CEI 4.0 standards.

Next Gen Development in Type-C Ecosystem

This session will cover the latest updates in the Type-C Ecosystem that includes USB, DP, and Thunderbolt.

Physical Layer Validation Challenges of Characterizing 100 Gbps/lane Designs

This session will be a practical discussion of IEEE 802.3ck (100Gbps/lane) physical layer conformal testing for both Tx and Rx. 100G silicon is emerging from the early specifications and a world of simulation. This track will help bridge the gap between simulation and physical layer evaluation of SERDES design and conformance testing.

Solving Your Forward Error Correction Problems

Forward Error Correction (FEC) can effectively eliminate data loss (frame loss) in systems with moderately high Bit Error Rates (BER) of 1E-4 or more. However, in real systems, errors sometimes occur in bursts and can lead to FEC failure and non-zero Frame Loss Ratio (FLR). This presentation will demonstrate a real-time oscilloscope combined with FEC-aware tester. This solution will be shown to trigger on, capture and debug burst errors, or uncorrectable FEC events that can lead to unexpected frame loss in 400GBASE-DR4 and 400GBASE-SR8 devices.

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