Power Amplifier Design
High-Speed Digital Design - On-Demand Webinars 
Applications like modern data centers and Artificial Intelligence (AI) drive the need for higher bandwidth of serial links and faster memory implementations. Latest SerDes technologies and DDR5 are aiming to multi Gigabit per second. Getting to a compliant design requires knowledge on voltage and timing margins as well as parasitics of the Printed Circuit Board (PCB). These webinars cover the latest in Signal and Power Integrity.
On-Demand Webinars
What You Need to Know Before Simulating DDR5 Buses
What You Need to Know Before Simulating DDR5 Buses

The desire for more bandwidth in data centers has led to intense pressure to push DDR5 memory technology out to market faster. During this webinar you will learn what you need to know before simulating DDR5 buses. 
How to Find the Elusive Dynamic Switching Current of Your FPGA Power Rail
How to Find the Elusive Dynamic Switching Current of Your FPGA Power Rail

Multipin FPGA devices soldered to a PCB make it impossible to attach the typical oscilloscope current clamp probe. This Keysight PathWave webinar will walk you through the methodology of combining voltage measurements across a power delivery network (PDN) combined with simulation of the PDN impedances to synthesise dynamic current at the FPGA pins. 
Evaluate Electrical Performance in Electrical-Optical-Electrical Link Systems
Evaluate Electrical Performance in Electrical-Optical-Electrical Link Systems

Data centers transport data using optical connections. To evaluate the system’s performance, consider the entire link condition, which includes the optical channel. In this webinar, we will introduce a real-time analysis method using PathWave Advanced Design System (ADS) and   VPIphotonics  TransmissionMaker optical solution to predict design margins, such as eye height and eye width, at the desired system bit error rate. 
DDR4 Edge System Design Challenges: Correlating Simulation and Measurements
DDR4 Edge System Design Challenges: Correlating Simulation and Measurements

Measuring DDR4/5 without signal restoration techniques will not be successful. Accurately predicting the quality of DDR signals on your Printed Circuit Board (PCB) will help to get to a DDR compliant implementation. This presentation illustrates the use of measurements and simulations to drive the verification of complex DDR4 systems to prepare the design and measurement flow for DDR5 
Reducing DDR4 Board Failures and Design Optimization Time
Reducing DDR4 Board Failures and Design Optimisation Time

SECO has adopted a design flow that minimises effort to set up simulations. It provides an entire high-speed digital design workflow and it uses the same measurement science for both simulation and hardware verification stages. As a result, they have been able to reduce design time and improve yield dramatically. 
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