Overcoming DDR challenges with DRAM AMI modeling

With DDR getting into the multi-gigabit range, we see memory systems adopting high-speed serial technologies. New memory devices are using equalization (e.g. DDR5) and/or multi-level modulations (e.g. DDR6X and GDDR7 with PAM4). As a result, designing with DDR becomes more challenging than ever before and standard signal integrity analysis is no longer sufficient.

As you need to regenerate your signal from a closed data eye-diagram due to the channel effects, Keysight is offering a design flow, which lets you:

Create and use JEDEC conform IBIS AMI models for DRAM drivers and receivers and easily connect them to the memory bus
Get full understanding of the channel characteristics through end-to-end simulations
Evaluate the design performance and margins of your DDR5 interface with IBIS-AMI modeling features such as Decision Feedback Equalization (DFE) and jitter tracking

Date: Thursday December 9, 2021

Time: 11:00 AM CET / 3:30PM IST

Duration: 1 hour

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PRESENTERS

Simon Muff

Application Engineer and Business Development Manager for High Speed Digital and Power Electronics

Keysight Technologies

Hermann Ruckerbauer

Owner of EyeKnowHow