DDR4 Edge System Design Challenges: Correlating Simulation and Measurements Webinar

DDR4 Edge System Design Challenges: Correlating Simulation and Measurements

Applications like modern data centers and Artificial Intelligence (AI) drive the need for new bandwidth and features in DDR Memory implementations. Measuring DDR4/5 without signal restoration techniques will not be successful. Accurately predicting and analysing the quality of DDR signals on your Printed Circuit Board (PCB) in simulation will help to get to a DDR compliant implementation. This presentation illustrates the use of measurement technologies and simulation approaches to drive the verification of complex DDR4 systems to prepare the design and measurement flow for DDR5.

Key learnings:

LPDDR/DDR memory probing including de-embedding
Simulating and analysing PCB effects on your design
Correlating simulation and measurements for DDR compliance

Duration: 1 hour

Available On Demand

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PRESENTER

Simon Muff

Application Engineer and Business Development Manager for High Speed Digital and Power Electronics

Keysight Technologies