Keysight will demo a physical design validation solution for 800G components and transceivers. 100G electrical interfaces such as those defined by the IEEE 802.3ck and OIF-CEI 112G standardization bodies are the workhorse of next generation datacenter. Because 53Gbaud PAM4 interface design margins are shrinking, the need for accurate in-depth design validation has increased tremendously. The solution consists of the M8040A BERT, combined with the G800GE multichannel tester. It is designed to integrate FEC constraints into the physical design validation and compliance testing.
100G Serial FEC Aware Conformance Testing highlights:
- System margin insights
- Measure frame loss ratio
- Error burst analysis